The processing unit (CPU) of a typical computer can process data much faster than the memory unit can store or retrieve that data. In order for the CPU to operate as efficiently as possible, an expensive (and fast) memory, called a cache memory, is used to try and keep up with the CPU. When the CPU needs to manipulate data which is not in the cache, it must then retrieve that data from the slower memory, which can cost perhaps 50 machine instruction cycles.
As processors become faster and faster, this problem becomes more severe, particularly because the speed of the processors is increasing faster than the speed of the memory. This problem is particularly solved by sending a data prefetch request to the cache ahead of time before the CPU actually needs the data. This is done by an instruction called a Data Prefetching Instruction. Such instructions are issued well ahead of time on the theory that by the time it is actually needed that data is already in cache and available to the CPU.
Doing such prefetching can be challenging, as prefetch instructions are inserted by the compiler, when the machine control code is compiled from the source instructions. Usually, such prefetch instructions are inserted in situations where there is a loop and the compiler can tell what is going to happen by virtue of a repeated sequence of memory accesses. The compiler determines that a loop is accessing data and looks at new accessing block "2" on a repetitive basis and then accesses data block "1" (data block "2" ) about 50 bytes away, (assuming that the pattern will continue).
In programs that do not have regular loop patterns, the optimizer is not able to put in the prefetch instructions because it cannot predict what the pattern of access of memory will be. In some situations, a user could insert prefetch instructions, but currently there is no automated way to put in prefetch instructions in situations where predictable loops do not exist.
Therefore, a need exists in the art for a system and method for bringing data in the data cache before that data is actually required where there is not a regular address pattern from which prefetching can be predicted.